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LCD Segment Driver series
Standard function Segment Drivers
BU9795AKV, BU9795AFV, BU9795AGUW
No.09044EBT01
Description This is LCD segment driver for 140 segment type display. There is a lineup which is suitable for multi function display and is integrated display RAM and power supply circuit for LCD driving with 4 common output type: BU9795AKV/FV/GUW. Features 1) 3wire serial interface (CSB, SD, SCL) 2) Integrated RAM for display data (DDRAM) : 35 x 4bit (Max 140 Segment) 3) LCD driving port: 4 Common output, Segment: 35output (BU9795AKV), 31output (BU9795AGUW), 27output (BU9795AFV) 4) Display duty: 1/4 duty 5) Integrated Buffer AMP for LCD driving power supply 6) 1/2bias, 1/3bias selectable 7) No external components 8) Low power/ Ultra low power consumption design: +2.55.5V
Applications Telephone, FAX, Portable equipment (POS, ECR, PDA etc.), DSC, DVC, Car audio, Home electrical appliance, Meter equipment etc. Line up matrix Parameter Segment output Common output Package BU9795AKV 35 4 VQFP48C BU9795AFV 27 4 SSOP-B40 BU9795AGUW 31 4 VBGA048W040
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1/15
2009.07 - Rev.B
BU9795AKV, BU9795AFV, BU9795AGUW
Absolute maximum ratings (Ta=25degree, VSS=0V) Parameter Power supply voltage1 Power supply voltage2
Symbol
Technical Note
Limits -0.5 +7.0 -0.5 VDD 0.6
Unit V V W W W V degree degree
Remark Power supply LCD drive voltage When use more than Ta=25C, subtract 6mW per degree.(BU9795AKV) When use more than Ta=25C, subtract 7mW per degree (BU9795AFV) When use more than Ta=25C, subtract 2.7mW per degree (BU9795AGUW)
VDD VLCD
Allowable loss
Pd
0.7 0.27
Input voltage range Operational temperature range Storage temperature range
VIN Topr Tstg
-0.5
VDD+0.5 +85 +125
-40 -55
*This product is not designed against radioactive ray. Operating conditions (Ta=25degree,VSS=0V) Parameter Symbol Min. Power Supply voltage1 VDD 2.5 Power Supply voltage2 VLCD 0 * Please use VDD-VLCD2.4V condition. Typ. Max. 5.5 VDD-2.4 Unit V V Remark Power supply LCD drive voltage
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2/15
2009.07 - Rev.B
BU9795AKV, BU9795AFV, BU9795AGUW
Technical Note
Electrical characteristics DC Characteristics (VDD=2.55.5V, VSS=0V, Ta=-4085degree, unless otherwise specified) Limit Symbol Unit Condition Parameter MIN TYP MAX VIH 0.7VDD VDD V "H" level input voltage VIL VSS 0.3VDD V "L" level input voltage IIH 1 uA "H" level input current IIL -1 uA "L" level input current SEG RON 3.5 k Iload=10uA LCD Driver on resistance COM RON 3.5 k VDD -2.4 VLCD supply voltage VLCD 0 V VDD-VLCD2.5V Display off, Oscillator off Ist 5 uA Standby current Power consumption 1 IDD1 12.5 30 uA VDD=3.3[V], Ta=25, Power save mode1, FR=70Hz 1/3 bias, Frame inverse VDD=3.3[V], Ta=25, Normal mode, FR=80Hz 1/3 bias, Line inverse
Power consumption 2
IDD2
-
20
40
uA
Oscillation Characteristics (VDD=2.55.5V,VSS=0V, Ta=-4085degree) Parameter Frame frequency Frame frequency1 Symbol fCLK fCLK1 MIN 56 70 Limit TYP 80 80 MAX 104 90 Unit Hz Hz Condition FR = 80Hz setting VDD=3.5V, 25degree
MPU interface Characteristics (VDD=2.5V5.5V,VSS=0V, Ta=-4085degree) Parameter Input rise time Input fall time SCL cycle time "H" SCL pulse width "L" SCL pulse width SD setup time SD hold time CSB setup time CSB hold time "H" CSB pulse width Symbol tr tf tSCYC tSHW tSLW tSDS tSDH tCSS tCSH tCHW MIN 400 100 100 20 50 50 50 50 Limit TYP MAX 80 80 Unit ns ns ns ns ns ns ns ns ns ns
tCHW
Condition
CSB
tCSS tf tSCYC tSLW tSHW tr tCSH
SCL SD
tSDS
tSDH
Fig.1 3wire Serial timing waveform
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3/15
2009.07 - Rev.B
BU9795AKV, BU9795AFV, BU9795AGUW
Technical Note
* BU9795AKV Block Diagram
COM0......COM3 VDD LCD voltage generator common driver Segment driver SEG0......SEG34
Pin Arrangement
SEG34
SEG33
SEG32
SEG31
SEG30
SEG29
SEG28
SEG27
SEG26
SEG25

COM1
LCD BIAS SELECTOR common counter blink timing generator DDRAM
37
SEG24 25
36 COM0
24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13
COM2 COM3 VLCD VDD VSS

VLCD
OSCIO CSB
INHb OSCIN OSCILLATOR Power On Reset Command register Command Data Decoder
SCL SD TEST
serial inter face
INHb
48
SEG12 13
TEST
CSB
SD
SCL
Fig. 2A BU9795AKV Block diagram Terminal description Terminal No. 48
Fig. 3A BU9795AKV Pin arrangement
Terminal INHb TEST
I/O I
Function Input terminal for turn off display H: turn on display L: turn off display Test input (ROHM use only) Must be connect to VSS External clock input Ex clock and Int clock can be changed by command. Must be connect to VSS when use internal oscillation circuit. serial data input serial data transfer clock Chip select GND Power supply Power supply for LCD driving : "L" active
47
43 46 45 44 42 41 40 1-35 36-39
I
I I I I
OSCIO SD SCL CSB VSS VDD VLCD SEG0-34 COM0-3
O O
SEGMENT output for LCD driving COMMON output for LCD driving
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4/15
SEG10
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
VSS
2009.07 - Rev.B
SEG11 12
1
IF FILTER
BU9795AKV, BU9795AFV, BU9795AGUW
* BU9795AFV Block Diagram
Technical Note
Pin Arrangement
COM0......COM3 VDD LCD voltage generator common driver
SEG4......SEG30
SEG30 SEG29 OSCIO SEG28 21 20 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG8 SEG9 VLCD COM3 COM2 COM1 COM0
TEST
SEG7
SEG6
SEG5
SEG4
INHb
CSB
Segment driver
40

LCD BIAS SELECTOR common counter blink timing generator DDRAM

1
VLCD
INHb OSCIN OSCILLATOR Pow er On Reset Command register Command Data Decoder
serial inter face
IF FILTER VSS
TEST
CSB
SD
SCL
Fig. 2B BU9795AFV Block diagram
Fig. 3B BU9795AFV Pin arrangement
Terminal description Terminal No. 36
Terminal INHb TEST
I/O I
Function Input terminal for turn off display H: turn on display L: turn off display Test input (ROHM use only) Must be connect to VSS External clock input Ex clock and Int clock can be changed by command. Must be connect to VSS when use internal oscillation circuit. serial data input serial data transfer clock Chip select GND Power supply : "L" active
35
31 34 33 32 30 29 28 1-23, 37-40 24-27
I
I I I I
OSCIO SD SCL CSB VSS VDD VLCD SEG4-30 COM0-3
I O O
Power supply for LCD driving SEGMENT output for LCD driving COMMON output for LCD driving
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SCL
VSS
VDD
SD
5/15
2009.07 - Rev.B
BU9795AKV, BU9795AFV, BU9795AGUW
Technical Note
* BU9795AGUW Block Diagram
Pin Arrangement
COM0......COM3 VDD LCD voltage generator common driver
SEG2......SEG32
1 G (NC)
2 SEG13
3 SEG15
4 SEG18
5 SEG20
6 SEG22
7 (NC)
Segment driver
F

SEG11
SEG12
SEG16
SEG17
SEG21
SEG23
SEG24
LCD BIAS SELECTOR common counter blink timing generator DDRAM
E
SEG9
SEG10
SEG14
SEG19
SEG25
SEG27
SEG26

D
VLCD
SEG7
SEG6
SEG8
SEG5
SEG30
SEG28
SEG29
C
INHb OSCIN OSCILLATOR Pow er On Reset Command register Command Data Decoder
SEG4
SEG3
SEG2
CSB
COM3
SEG32
SEG31
B
INHb
SD
VSS
VDD
COM1
COM0
serial inter face
A
IF FILTER VSS
(NC)
TEST2
SCL
OSCIO
VLCD
COM2
(NC)
TEST
CSB
SD
SCL
Fig. 2C BU9795AGUW Block diagram
Fig. 3C BU9795AGUW Pin arrangement
Terminal description Terminal INHb TEST I/O I Function Input terminal for turn off display H: turn on display L: turn off display Test input (ROHM use only) Must be connect to VSS External clock input Ex clock and Int clock can be changed by command. Must be connect to VSS when use internal oscillation circuit. serial data input serial data transfer clock Chip select GND Power supply I O O Power supply for LCD driving SEGMENT output for LCD driving COMMON output for LCD driving : "L" active
I
I I I I
OSCIO SD SCL CSB VSS VDD VLCD SEG2-32 COM0-3
(Caution) About terminal number, please refer to above pin arrangement
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6/15
2009.07 - Rev.B
BU9795AKV, BU9795AFV, BU9795AGUW
Command Description D7 (MSB) is bit for command or data judgment. Refer to Command and data transfer method. C: 0: Next byte is RAM write data. 1: Next byte is command.
Technical Note
Mode Set (MODE SET)
MSB D7 C LSB D0 *
D6 1
D5 0
D4 *
D3 P3
D2 P2
D1 *
(*:Don't care)
Set display ON and OFF Setting Display OFF (DISPOFF) Display ON (DISPON) Set bias level Setting 1/3 Bias 1/2 Bias P2 0 1 Reset initialize condition P3 0 1 Reset initialize condition
Address set (ADSET)
MSB D7 C D6 0 D5 0 D4 P4 D3 P3 D2 P2 D1 P1 LSB D0 P0
Address data is specified in P[4:0] and P2 (ICSET command) as follows.
Internal register Bit of each command MSB Address [5] ICSET [P2] Address [4] ADSET [P4] LSB Address [0] ADSET [P0]
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7/15
2009.07 - Rev.B
BU9795AKV, BU9795AFV, BU9795AGUW
Display control (DISCTL)
MSB D7 C D6 0 D5 1 D4 P4 D3 P3 D2 P2 D1 P1 LSB D0 P0
Technical Note
Set Frame frequency Setting 80Hz 71Hz 64Hz 53Hz Set LCD drive waveform Setting Line inversion Frame inversion Set Power save mode Setting Power save mode 1 Power save mode 2 Normal mode High power mode P1 0 0 1 1 P0 0 1 0 1 Reset initialize condition P2 0 1 Reset initialize condition P4 0 0 1 1 P3 0 1 0 1 Reset initialize condition
VDD-VLCD>=3.0V is required for High power mode.
Set IC Operation (ICSET)
MSB D7 C D6 1 D5 1 D4 0 D3 1 D2 P2 D1 P1 LSB D0 P0
P2: MSB data of DDRAM address. Please refer to "ADSET" command.
Setting Address MSB`0' Address MSB`1' Set Software Reset condition Setting No operation Software Reset P1 0 1 P2 0 1 Reset initialize condition
Switch between internal clock and external clock.
Setting Internal clock External clock input P0 0 1 Reset initialize condition
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8/15
2009.07 - Rev.B
BU9795AKV, BU9795AFV, BU9795AGUW
Blink control (BLKCTL)
MSB D7 C D6 1 D5 1 D4 1 D3 0 D2 * D1 P1 LSB D0 P0
Technical Note
Set blink condition Setting OFF 0.5 Hz 1 Hz 2 Hz P1 0 0 1 1 P0 0 1 0 1 Reset initialize condition
All pixel control (APCTL) MSB D7 C D6 1 D5 1 D4 1 D3 1 D2 1 D1 P1 LSB D0 P0
All display set ON. OFF Setting Normal All pixel ON P1 0 1 Reset initialize condition
Setting Normal All pixel OFF
P0 0 1
Reset initialize condition
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9/15
2009.07 - Rev.B
BU9795AKV, BU9795AFV, BU9795AGUW
Function description Command and data transfer method 3-SPI (3wire Serial interface)
Technical Note
This device is controlled by 3-wire signal (CSB, SCL, and SD). First, Interface counter is initialized with CSB="H", and CSB="L" makes SD and SCL input enable. The protocol of 3-SPI transfer is as follows. Each command starts with Command or Data judgment bit (D/C) as MSB data, and continuously in order of D6 to D0 are followed after CSB ="L". (Internal data is latched at the rising edge of SCL, it converted to 8bits parallel data at the falling edge of 8th CLK.)
Command CSB SCL SD D/C D6 D5 D4 D3 D2 D1 D0 D/C D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 Command/Data
D/C = "H" : Command D/C = "L" : Data
Fig. 4 3-SPI Command/Data transfer format
Write display data and transfer method
* BU9795AKV
This LSI have Display Data RAM (DDRAM) of 35x4=140bit. The relationship between data input and display data, DDRAM data and address are as follows.
Command 0000000 a b cd e f g h i jk lm n op ...
Display Data
8 bit data will be stored in DDRAM. The address to be written is the address specified by Address set command, and the address is automatically incremented in every 4bit data. Data can be continuously written in DDRAM by transmitting Data continuously. (When RAM data is written successively after writing RAM data to 22h (SEG34), the address is returned to 00h (SEG0) by the auto-increment function.
DDRAM address
00h 01h 02h 03h 04h 05h 06h 07h
1Eh
1Fh
20h
21h
22h COM0 COM1 COM2 COM3
0 1 BIT 2 3
a b c d
SEG0
e f g h
SEG1
i j k l
SEG2
m n o p
SEG3
q r s t
SEG4
u v x y
SEG5 SEG6 SEG7 SEG30 SEG31 SEG32 SEG33 SEG34
As data transfer to DDRAM happens every 4bit data, it will be cancelled if it changes CSB="L""H" before 4bits data transfer.
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10/15
2009.07 - Rev.B
BU9795AKV, BU9795AFV, BU9795AGUW
* BU9795AFV
Technical Note
As SEG0, SEG1, SEG2, SEG3, SEG31, SEG32, SEG33, SEG34 are not output, these address will be
dummy address. Dummy data 00h 01h 02h 03h 04h 05h
DDRAM address
06h 07h
Dummy data
1Eh
1Fh
20h
21h
22h COM0 COM1 COM2 COM3
0 1 BIT 2 3
a b c d
SEG0
e f g h
SEG1
i j k l
SEG2
m n o p
SEG3
q r s t
SEG4
u v x y
SEG5 SEG6 SEG7 SEG30 SEG31 SEG32 SEG33 SEG34
As data transfer to DDRAM happens every 4bit data, it will be cancelled if it changes CSB="L""H" before 4bits data transfer.
* BU9795AGUW
As SEG0, SEG1, SEG33, SEG34 are not output, these address will be dummy address.
Dummy data 00h 01h 02h 03h 04h 05h
DDRAM address
06h 07h
Dummy data
1Eh
1Fh
20h
21h
22h COM0 COM1 COM2 COM3
0 1 BIT 2 3
a b c d
SEG0
e f g h
SEG1
i j k l
SEG2
m n o p
SEG3
q r s t
SEG4
u v x y
SEG5 SEG6 SEG7 SEG30 SEG31 SEG32 SEG33 SEG34
As data transfer to DDRAM happens every 4bit data, it will be cancelled if it changes CSB="L""H" before 4bits data transfer.
Reset (initial)
condition Initial condition after execute Software Reset is as follows. Display is OFF. DDRAM address is initialized (DDRAM Data is not initialized). Refer to Command Description about initialize value of register.
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11/15
2009.07 - Rev.B
BU9795AKV, BU9795AFV, BU9795AGUW
Technical Note
Cautions of Power-On condition
This LSI has "P.O.R" (Power-On Reset) circuit and Software Reset function. Please keep the following recommended Power-On conditions in order to power up properly.
1. Please set power up conditions to meet the recommended tR, tF, tOFF, and Vbot spec below in order to ensure P.O.R operation.
VDD
tF
tR
Recommendation condition of tR,tF,tOFF,Vbot
tR Less than 1ms tF Less than 1ms tOFF More than 150ms Vbot Less than 0.1V
tOFF
Vbot
Power
ON/OFF
Fig. 5 Power on-off waveform 2.
If it is difficult to meet above conditions, execute the following sequence after Power-On. Because it doesn't accept the command in power off, it is necessary to care that correspondence by software reset doesn't become alternative to POR function completely.
(1)
CSB="L""H" condition
VDD
CS B
Fig. 6 CSB Timing (2) IO Circuit
After CSB"H""L", execute Software Reset (ICSET command).
(BU9795AKV /AFV /AGUW)
VDD VLCD VSS VDD TEST VSS
VDD
VDD OSCIN
CSB, SD, SCL VSS
VSS
VDD VDD INHb
VSS
VSS
Fig. 7
IO circuit
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12/15
2009.07 - Rev.B
BU9795AKV, BU9795AFV, BU9795AGUW
Technical Note
Notes for Application (BU9795AKV /BU9795AFV / BU9795AGUW) In case, BU9795AKV/ BU9795AFV/ BU9795AGUW used at VLCDVSS, voltage gap occur between SEG line to COM1 - 3 line at Display off state. Because of this voltage gap, there is possibility to display LCD for a moment. To avoid this phenomenon, please decide VDD and VLCD level to satisfy Voff voltage lower than OFF level (OFF level = 1V at the example explained below).
condition VDD=5.0V VLCD=2.0V 1/3bias DDRAM data ALL "H" Frame inversion
In case, VLCD voltage different from VSS levelVLCDVSS) In this case, volatage gap occur, between SEG line to COM 1-3 line. Because of this gap, there is possibility to display LCD for a moment.
1Frame Send "Display off" command
VDD (5V)
SEG0 Output
VLCD (2V)
Output VLCD level at display off All SEG terminal
VLCD-VSS=2V VSS
COM0 Output
VDD (5V)
Output VLCD level at display off Only COM0 terminal VLCD (2V)
VLCD-VSS=2V VSS
COM1 Output
VDD (5V)
VLCD (2V)
Output VSS level at display off (at COM 1-3 terminal) VLCD-VSS=2V
VSS
Display on
Display off
Voltage gap of COM0-SEG0
3V 2V 1V 0V -1V -2V -3V the volatage between COM0 to SEG0 is 0V at display off.
Display on
Display off
Voltage gap of COM1-SEG0
3V 2V 1V 0V -1V -2V -3V Voltage gap occur between COM1 to SEG0 at display off. So, there is possibility to display LCD. Only at COM 1-3 line
ON level
the volatage between COM1 to SEG0 is -2V at display off.
OFF level Voff
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13/15
2009.07 - Rev.B
BU9795AKV, BU9795AFV, BU9795AGUW
Notes for use
Technical Note
(1) Absolute Maximum Ratings An excess in the absolute maximum ratings, such as supply voltage, temperature range of operating conditions, etc., can break down devices, thus making impossible to identify breaking mode such as a short circuit or an open circuit. If any special mode exceeding the absolute maximum ratings is assumed, consideration should be given to take physical safety measures including the use of fuses, etc. (2) Operating conditions These conditions represent a range within which characteristics can be provided approximately as expected. The electrical characteristics are guaranteed under the conditions of each parameter. (3) Reverse connection of power supply connector The reverse connection of power supply connector can break down ICs. Take protective measures against the breakdown due to the reverse connection, such as mounting an external diode between the power supply and the IC's power supply terminal. (4) Power supply line Design PCB pattern to provide low impedance for the wiring between the power supply and the GND lines. In this regard, or the digital block power supply and the analog block power supply, even though these power supplies has the same level of potential, separate the power supply pattern for the digital block from that for the analog block, thus suppressing the diffraction of digital noises to the analog block power supply resulting from impedance common to the wiring patterns. For the GND line, give consideration to design the patterns in a similar manner. Furthermore, for all power supply terminals to ICs, mount a capacitor between the power supply and the GND terminal. At the same time, in order to use an electrolytic capacitor, thoroughly check to be sure the characteristics of the capacitor to be used present no problem including the occurrence of capacity dropout at a low temperature, thus determining the constant. (5) GND voltage Make setting of the potential of the GND terminal so that it will be maintained at the minimum in any operating state. Furthermore, check to be sure no terminals are at a potential lower than the GND voltage including an actual electric transient. (6) Short circuit between terminals and erroneous mounting In order to mount ICs on a set PCB, pay thorough attention to the direction and offset of the ICs. Erroneous mounting can break down the ICs. Furthermore, if a short circuit occurs due to foreign matters entering between terminals or between the terminal and the power supply or the GND terminal, the ICs can break down. (7) Operation in strong electromagnetic field Be noted that using ICs in the strong electromagnetic field can malfunction them. (8) Inspection with set PCB On the inspection with the set PCB, if a capacitor is connected to a low-impedance IC terminal, the IC can suffer stress. Therefore, be sure to discharge from the set PCB by each process. Furthermore, in order to mount or dismount the set PCB to/from the jig for the inspection process, be sure to turn OFF the power supply and then mount the set PCB to the jig. After the completion of the inspection, be sure to turn OFF the power supply and then dismount it from the jig. In addition, for protection against static electricity, establish a ground for the assembly process and pay thorough attention to the transportation and the storage of the set PCB. (9) Input terminals In terms of the construction of IC, parasitic elements are inevitably formed in relation to potential. The operation of the parasitic element can cause interference with circuit operation, thus resulting in a malfunction and then breakdown of the input terminal. Therefore, pay thorough attention not to handle the input terminals, such as to apply to the input terminals a voltage lower than the GND respectively, so that any parasitic element will operate. Furthermore, do not apply a voltage to the input terminals when no power supply voltage is applied to the IC. In addition, even if the power supply voltage is applied, apply to the input terminals a voltage lower than the power supply voltage or within the guaranteed value of electrical characteristics. (10) Ground wiring pattern If small-signal GND and large-current GND are provided, It will be recommended to separate the large-current GND pattern from the small-signal GND pattern and establish a single ground at the reference point of the set PCB so that resistance to the wiring pattern and voltage fluctuations due to a large current will cause no fluctuations in voltages of the small-signal GND. Pay attention not to cause fluctuations in the GND wiring pattern of external parts as well. (11) External capacitor In order to use a ceramic capacitor as the external capacitor, determine the constant with consideration given to a degradation in the nominal capacitance due to DC bias and changes in the capacitance due to temperature, etc. (12) No Connecting input terminals In terms of extremely high impedance of CMOS gate, to open the input terminals causes unstable state. And unstable state brings the inside gate voltage of p-channel or n-channel transistor into active. As a result, battery current may increase. And unstable state can also causes unexpected operation of IC. So unless otherwise specified, input terminals not being used should be connected to the power supply or GND line. (13) Rush current When power is first supplied to the CMOS IC, it is possible that the internal logic may be unstable and rush current may flow instantaneously. Therefore, give special condition to power coupling capacitance, power wiring, width of GND wiring, and routing of connections.
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14/15
2009.07 - Rev.B
BU9795AKV, BU9795AFV, BU9795AGUW
Ordering part number
Technical Note
B
D
9
Part No.
7
9
5
A
K
V
-
E
2
Part No.
Package KV: VQFP48C FV: SSOP-B40 GUW: VBGA048W040
Packaging and forming specification E2: Embossed tape and reel
VQFP48C
9.00.2 7.00.1
36 37 25 24

Tape Quantity Embossed carrier tape 1500pcs E2
direction the at left when you ( The on the leftishand1pin of product is thethe upperthe right hand hold ) reel and you pull out tape on
9.0 0.2
7.0 0.1
48 1 12
13
0.75
1.6MAX
1PIN MARK
+0.05 0.145 -0.03
4 +6 -4
1.4 0.05 0.1 0.05
0.50.1
0.08 S +0.05 0.22 -0.04 0.08
0.50.15
1.00.2
0.75
Direction of feed
M
1pin
Direction of feed
(Unit : mm)
Reel
Order quantity needs to be multiple of the minimum quantity.
SSOP-B40

13.6 0.2 (MAX 13.95 include BURR)
Tape Quantity
21
Embossed carrier tape 2000pcs E2
The direction is the 1pin of product is at the upper left when you hold
40
7.8 0.3
5.4 0.2
1
20
1.8 0.1
0.15 0.1
0.1
0.1 0.65 0.22 0.1 0.08
M
S
0.5 0.2
Direction of feed
( reel on the left hand and you pull out the tape on the right hand
)
1pin
(Unit : mm)
Direction of feed
Reel
Order quantity needs to be multiple of the minimum quantity.
VBGA048W040
4.00.1

Tape
4.0 0.1
Embossed carrier tape (with dry pack) 2500pcs E2
The direction is the 1pin of product is at the upper left when you hold
Quantity Direction of feed
S
1PIN MARK
48- 0.2950.05 0.05 M S AB
P=0.5x6 A 0.5
B
G F E D C B A 1234 567
0.5 P=0.5 x 6
0.5 0.1
0.08 S 0.50.1
0.10 0.9MAX
( reel on the left hand and you pull out the tape on the right hand
)
1pin
Direction of feed
(Unit : mm)
Reel
Order quantity needs to be multiple of the minimum quantity.
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15/15
2009.07 - Rev.B
Notice
Notes
No copying or reproduction of this document, in part or in whole, is permitted without the consent of ROHM Co.,Ltd. The content specified herein is subject to change for improvement without notice. The content specified herein is for the purpose of introducing ROHM's products (hereinafter "Products"). If you wish to use any such Product, please be sure to refer to the specifications, which can be obtained from ROHM upon request. Examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage and operations of the Products. The peripheral conditions must be taken into account when designing circuits for mass production. Great care was taken in ensuring the accuracy of the information specified in this document. However, should you incur any damage arising from any inaccuracy or misprint of such information, ROHM shall bear no responsibility for such damage. The technical information specified herein is intended only to show the typical functions of and examples of application circuits for the Products. ROHM does not grant you, explicitly or implicitly, any license to use or exercise intellectual property or other rights held by ROHM and other parties. ROHM shall bear no responsibility whatsoever for any dispute arising from the use of such technical information. The Products specified in this document are intended to be used with general-use electronic equipment or devices (such as audio visual equipment, office-automation equipment, communication devices, electronic appliances and amusement devices). The Products specified in this document are not designed to be radiation tolerant. While ROHM always makes efforts to enhance the quality and reliability of its Products, a Product may fail or malfunction for a variety of reasons. Please be sure to implement in your equipment using the Products safety measures to guard against the possibility of physical injury, fire or any other damage caused in the event of the failure of any Product, such as derating, redundancy, fire control and fail-safe designs. ROHM shall bear no responsibility whatsoever for your use of any Product outside of the prescribed scope or not in accordance with the instruction manual. The Products are not designed or manufactured to be used with any equipment, device or system which requires an extremely high level of reliability the failure or malfunction of which may result in a direct threat to human life or create a risk of human injury (such as a medical instrument, transportation equipment, aerospace machinery, nuclear-reactor controller, fuel-controller or other safety device). ROHM shall bear no responsibility in any way for use of any of the Products for the above special purposes. If a Product is intended to be used for any such special purpose, please contact a ROHM sales representative before purchasing. If you intend to export or ship overseas any Product or technology specified herein that may be controlled under the Foreign Exchange and the Foreign Trade Law, you will be required to obtain a license or permit under the Law.
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